The integration of carbon nanostructures as channel materials in the next generation of electronic devices offers many advantages over the continued scaling of silicon (Si). Carbon nanotubes and graphene are two nanoscale forms of carbon that exhibit extremely high current carrying capacity and mobilities several orders of magnitude beyond the theoretical limit for Si. Additionally, carbon nanotubes (one-dimensional) and graphene (two-dimensional) are low-dimensional (ultra thin-body) materials, allowing them to be aggressively scaled in field-effect transistors without incurring deleterious short-channel effects that hinder modem scaled devices. See, for example, J. Appenzeller, “Carbon Nanotubes for High-Performance Electronics-Progress and Prospect,” Proceedings of the IEEE, vol. 96, no. 2, pp. 201-211 (February 2008), the contents of which are incorporated by reference herein.
One of the foremost challenges to scaling either of these nanomaterials is the difficulty of establishing thin, uniform and high-quality dielectrics on their surfaces. The surface of both materials consists of strong sp2 carbon bonds with nominally no surface states. The absence of open surface bonds makes it nearly impossible to nucleate or deposit insulators, especially with the monolayer accuracy that is needed for scaled gate dielectrics. Approaches to overcoming this obstacle thus far have involved 1) gas-phase functionalization of the carbon surface with a noncovalent monolayer (see, for example, D. Farmer et al., “Atomic Layer Deposition on Suspended Single-Walled Carbon Nanotubes via Gas-Phase Noncovalent Functionalization,” Nano Letts., 6(4): 699-703 (2006), the contents of which are incorporated by reference herein), 2) wrapping of carbon nanotubes with molecules (see, for example, Y. Lu et al., “DNA Functionalization of Carbon Nanotubes for Ultrathin Atomic Layer Deposition of High k Dielectrics for Nanotube Transistors with 60 mV/Decade Switching,” JACS, vol. 128, pp. 3518-3519 (2006), the contents of which are incorporated by reference herein), 3) overgrowth of dielectric layers to encompass carbon nanotubes (see, for example, A. Javey et al. “High-k Dielectrics for Advanced Carbon-Nanotube Transistors and Logic Gates,” Nature Mater., vol. 1, 241-246 (2002), the contents of which are incorporated by reference herein) and 4) deposition of thin (less than two nanometers (nm)) metal followed by its oxidation (see, for example, S. Kim et al., “Realization of a High Mobility Dual-Gated Graphene Field-Effect Transistor with Al2O3 Dielectric,” Applied Physics Letters, vol. 94, pp. 062107 (2009), the contents of which are incorporated by reference herein). All of these approaches are completed by the atomic layer deposition (ALD) of a high-k dielectric.
The first two approaches provide for good uniformity and dielectrics down to about two nm in thickness have been reported. However, the molecular layers have been shown to interact with the carbon bonds, creating scattering centers that cause the mobility to suffer greatly. In fact, since all carriers are on the surface of these nanostructures, the carriers strongly couple to any material that is deposited around them, causing degradation of the transport properties. Additionally, when using molecules such as deoxyribonucleic acid (DNA) to create a nucleation layer around carbon nanotubes the uniformity can be compromised as a result of the relatively large molecule diameter (four nm for DNA) compared to the carbon nanotubes (about 1.5 nm). The last two approaches provide no scheme for scaling the thickness of the dielectric, i.e., from about eight nm to about 15 nm of dielectric is necessary to ensure complete coverage of the carbon surface.
Therefore, device fabrication techniques that avoid the above-described problems associated with forming thin, uniform and high-quality dielectrics on the surfaces of nanomaterials would be desirable.